selected publications
-
academic article
- CoEx. ACM Transactions on Reconfigurable Technology and Systems. 8:1-16. 2015
- Optimized Communication Architecture of MPSoCs with a Hardware Scheduler. International Journal of Embedded and Real-time Communication Systems. 2:1-20. 2011
- A Scalable VLSI Architecture for Soft-Input Soft-Output Single Tree-Search Sphere Decoding. IEEE Transactions on Circuits and Systems Ii-express Briefs. 57:706-710. 2010
- Automatic Generation of Memory Interfaces for ASIPs. International Journal of Embedded and Real-time Communication Systems. 1:1-23. 2010
- Virtual architecture mapping: a SystemC based methodology for architectural exploration of System-on-Chips. International Journal of Embedded Systems. 3:150-150. 2008
- SHAPES - a Scalable Parallel HW/SW Architecture Applied to Wave Field Synthesis 2007
- Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. Journal of VLSI signal processing. 43:235-246. 2006
- Retargetable compilers and architecture exploration for embedded processors. IEE proceedings. 152:209-209. 2005
- Compiler design issues for embedded processors. IEEE Design & Test of Computers. 19:51-58. 2002
- Application specific compiler/architecture codesign. Sigplan Notices. 37:185-193. 2002
-
blog posting
- Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators. arXiv (Cornell University). 2020
-
book
-
chapter
- Optimized Communication Architecture of MPSoCs with a Hardware Scheduler. IGI Global eBooks. 163-180. 2013
- Automatic Generation of Memory Interfaces for ASIPs. IGI Global eBooks. 79-100. 2012
- Case Studies. Springer eBooks. 193-206. 2011
- ISA Customization Design Flow. Springer eBooks. 111-130. 2011
- Introduction. Springer eBooks. 1-4. 2010
- Processor Designer. Springer eBooks. 45-55. 2009
- CASE STUDIES: LEGACY CODE REUSE. Springer eBooks. 135-148. 2007
- Application Code Profiling and ISA Synthesis on MIPS 32. . 2007
- ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study. Lecture Notes in Computer Science. 2004
- Early ISS Integration into Network-on-Chip Designs. Springer eBooks. 443-452. 2004
- Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. Lecture Notes in Computer Science. 463-473. 2004
- Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs. Lecture Notes in Computer Science. 2004
- Architecture Exploration. Springer eBooks. 55-77. 2002
- Architecture Implementation. Springer eBooks. 79-100. 2002
- LISA Processor Design Platform. . 2002
- Processor Models for ASIP Design. . 2002
- Software Tools for Application Design. . 2002
- Traditional ASIP Design Methodology. . 2002
-
conference paper
- Entropy-Based Analysis of Benchmarks for Instruction Set Simulators. . 2023
- NEUROTEC I: Neuro-inspired Artificial Intelligence Technologies for the Electronics of the Future. 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2022
- Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators. . 2021
- Fast SystemC Processor Models with Unicorn. . 2019
- A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design. . 2019
- Application-Specific Architecture Exploration Based on Processor-Agnostic Performance Estimation. . 2015
- A novel reduced-complexity soft-input soft-output MMSE MIMO detector: Algorithm and efficient VLSI architecture. . 2014
- CoEx: A novel profiling-based algorithm/architecture co-exploration for ASIP design. . 2013
- Optimized communication architecture of MPSoCs with a hardware scheduler: A system view. . 2010
- Automatic generation of memory interfaces. . 2009
- High-level modelling and exploration of coarse-grained re-configurable architectures. . 2008
- High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures. 2008 Design, Automation and Test in Europe. 2008
- Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors. Proceedings. 2007
- Design space exploration of partially re-configurable embedded processors. Design, Automation, and Test in Europe. 319-324. 2007
- Instruction Set Customization of Application Speci.c Processors for Network Processing: A Case Study. . 2006
- Optimization Techniques for ADL-Driven RTL Processor Synthesis. . 2006
- C Compiler Retargeting Based on Instruction Semantics Models. Design, Automation, and Test in Europe. 2005
- Fine-grained application source code profiling for ASIP design. . 2005
- A methodology and tool suite for C compiler generation from ADL processor models. Proceedings Design, Automation and Test in Europe Conference and Exhibition. 2004
- A methodology and tool suite for C compiler generation from ADL processor models. . 21276-21276. 2004
- A system level processor/communication co-exploration methodology for multi-processor system-on-chip platforms. . 21256. 2004
- RTL processor synthesis for architecture exploration and implementation. . 30156. 2004
- Instruction encoding synthesis for architecture exploration using hierarchical processor models. . 2003
- A modular simulation framework for architectural exploration of on-chip interconnection networks. . 2003
- A modular simulation framework for architectural exploration of on-chip interconnection networks. . 2003
- Application specific compiler/architecture codesign. . 2002