selected publications

• academic article

  • A fast and compact classifier based on sorting in an iteratively expanded input space.  International Journal of Intelligent Systems.  23:607-618. 2008
  • The simplicial neural cell and its mixed-signal circuit implementation: an efficient neural-network architecture for intelligent signal processing in portable multimedia applications.  IEEE Transactions on Neural Networks.  13:995-1008. 2002

• chapter

  • Dynamically Reconfigurable Systems for Wireless Sensor Networks.  Springer eBooks. 315-334. 2010
  • PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels.  Lecture Notes in Computer Science. 2009
  • Hinoc: A Hierarchical Generic Approach for on-Chip Communication, Testing and Debugging of SoCs.  Kluwer Academic Publishers eBooks. 39-54. 2006
  • A Dynamically Reconfigurable Function-Unit for Error Detection and Correction in Mobile Terminals.  Lecture Notes in Computer Science. 2004
  • The XPP Architecture and Its Co-simulation Within the Simulink Environment.  Springer eBooks. 761-770. 2004
  • Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures.  Lecture Notes in Computer Science. 584-589. 2001
  • DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communication Applications.  Springer eBooks. 312-321. 2000
  • Field Programmable Communication Emulation and Optimization for Embedded System Design.  Lecture Notes in Computer Science. 2000
  • A New Approach for Designing Fault-Tolerant Array Processors.  Informatik-Fachberichte. 1991
  • Defect Tolerance in a Wafer Scale Array for Image Processing.  Springer eBooks. 327-338. 1989

• conference paper

  • (GECO)²: A graphical tool for the generation of configuration bitstreams for a smart sensor interface based on a Coarse-Grained Dynamically Reconfigurable Architecture.  . 2012
  • Mechanisms and Architecture for the Dynamic Reconfiguration of an Advanced Wireless Sensor Node.  . 2011
  • Design and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodes.  . 2009
  • CONFIGURABLE VLSI ARCHITECTURE OF A GENERAL PURPOSE LIFTING-BASED WAVELET PROCESSOR.  . 2008
  • High-performance floating-point VLSI architecture of a lifting-based wavelet processor.  . 2008
  • SPP1148 booth: Application-specific reconfigurable processors.  . 2008
  • A Scalable Resampling Architecture.  . 2007
  • An Efficient Fractional-Rate Interpolation Architecture.  . 2007
  • An efficient hardware implementation of a self-adaptable equalizer for WCDMA downlink UMTS standard.  . 2006
  • A state-serial Viterbi decoder architecture for digital radio on FPGA.  . 2006
  • Optimal FFT architecture selection for ofdm receivers on FPGA.  . 2006
  • HW/SW design and realization of a size-reconfigurable DCT accelerator.  . 2005
  • On-chip communication topology synthesis for shared multi-bus based architecture.  . 2005
  • Buffer-Architecture Exploration for Routers in a Hierarchical Network-on-Chip.  . 2005
  • A Compact Sequential Classifier for Digital Implementations.  . 2005
  • Performance aware on-chip communication synthesis and optimization for shared multi-bus based architecture.  . 2005
  • SORT: a fast and compact neural classifier based on a sorting preprocessor.  . 2004
  • A configurable pipelined state machine as a hybrid ASIC and configurable architecture.  IEEE Computer Society Annual Symposium on VLSI. 2004
  • Adaptive architectures for an OTN processor.  . 2004
  • Power estimation based on transition activity analysis with an architecture precise rapid prototyping system.  . 2003
  • Communication performance models for architecture-precise prototyping of real-time embedded systems.  . 2003
  • A parallel architecture for rapid prototyping of mechatronic algorithms by exploiting implicit fine-grain parallelism.  . 2002
  • Design and implementation of a coarse-grained dynamically reconfigurable hardware architecture.  . 2002
  • Automated communication synthesis for architecture-precise rapid prototyping of real-time embedded systems.  . 2002
  • An Application-Tailored Dynamically Reconfigurable Hardware Architecture for Digital Baseband Processing.  Symposium on Integrated Circuits and Systems Design. 341-346. 2000
  • A new flexible architecture for variable length DCT targeting shape-adaptive transform.  . 1999
  • Design and test of MEMS.  . 1999
  • Automatic transfer of parametric FEM models into CAD-layout formats for top-down design of microsystems.  European Design and Test Conference. 200-204. 1997
  • Multiway netlist partitioning onto FPGA-based board architectures.  European Design Automation Conference. 150-155. 1995
  • CAD framework concept for the design of integrated microsystems.  . 1995
  • A general CAD concept and design framework architecture for integrated microsystems.  HAL (Le Centre pour la Communication Scientifique Directe). 1995