selected publications

• academic article

  • Classification of Resilience Techniques Against Functional Errors at Higher Abstraction Layers of Digital Systems.  ACM Computing Surveys.  50:1-38. 2017
  • A Family of Modular QRD-Accelerator Architectures and Circuits Cross-Layer Optimized for High Area- and Energy-Efficiency.  Journal of Signal Processing Systems.  83:329-356. 2015
  • Application Domain Specific Embedded FPGAs for Flexible ISA-Extension of ASIPs.  Journal of Signal Processing Systems.  53:129-143. 2008
  • Design and quantitative analysis of parametrisable eFPGA-architectures for arithmetic.  Advances in Radio Science.  4:251-257. 2006
  • Performance analysis of general purpose and digital signal processor kernels for heterogeneous systems-on-chip.  Advances in Radio Science.  1:171-175. 2003

• chapter

  • ASIP-eFPGA Architecture for Multioperable GNSS Receivers.  Springer eBooks. 136-145. 2008

• conference paper

  • A family of modular area- and energy-efficient QRD-accelerator architectures.  . 2013
  • Interconnect routing of embedded FPGAs using standard VLSI routing tools.  . 2010
  • Design flow for embedded FPGAs based on a flexible architecture template.  . 2008
  • SPP1148 booth: Application-specific reconfigurable processors.  . 2008
  • Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers.  . 2007
  • A Parametrizable Low-Power High-Throughput Turbo-Decoder.  . 2006
  • Optimization of device dimensions for high-performance low-power architecture blocks.  . 2004
  • Analysis of reconfigurable and heterogeneous architectures in the communication domain.  . 2003
  • A new scalable VLSI architecture for Reed-Solomon decoders.  . 2002
  • Architecture and implementation of a bitserial sorter for weighted median filtering.  . 2002
  • CORDIC Processor with Carry-Save Architecture.  European Solid-State Circuits Conference. 193-196. 1990