selected publications

• chapter

  • Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture.  Lecture Notes in Computer Science. 2009
  • Low–Level Space Optimization of an AES Implementation for a Bit–Serial Fully Pipelined Architecture.  IFIP advances in information and communication technology. 2009
  • Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture.  Lecture Notes in Computer Science. 448-457. 2005

• conference paper

  • State-Based Real-Time Analysis for Function Networks and Marte.  . 2015
  • Optimization techniques for a reconfigurable, self-timed, and bit-serial architecture.  . 2007
  • Towards the Implementation of Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture.  . 2006