selected publications

• academic article

  • Pipelined architecture for fast CMOS buffer RAMs.  IEEE Journal of Solid-state Circuits.  25:741-747. 1990
  • A multiprocessor system for simulating data transmission systems (MUPSI).  Microprocessing and Microprogramming.  12:267-277. 1983

• chapter

  • FPGA-Efficient Hybrid LUT/CORDIC Architecture.  Springer eBooks. 933-937. 2004

• conference paper

  • Hierarchical architecture for fast CMOS SRAMs.  . 2003
  • Pipelined 16k Buffer RAM with 300MHz Operating Frequency.  . 1989