selected publications

• academic article

  • Network Architectures for Demanding 5G Performance Requirements: Tailored Toward Specific Needs of Efficiency and Flexibility.  IEEE Vehicular Technology Magazine.  14:33-43. 2019
  • Wireless-Optical Network Convergence: Enabling the 5G Architecture to Support Operational and End-User Services.  IEEE Communications Magazine.  55:184-192. 2017
  • Latency Critical IoT Applications in 5G: Perspective on the Design of Radio Interface and Network Architecture.  IEEE Communications Magazine.  55:70-78. 2017
  • Efficient Architecture for Soft-Input Soft-Output Sphere Detection With Perfect Node Enumeration.  IEEE Transactions on Very Large Scale Integration Systems.  24:2932-2945. 2016

• chapter

  • Code Generation for STA Architecture.  Lecture Notes in Computer Science. 299-310. 2006
  • Synchronous Transfer Architecture (STA).  Springer eBooks. 343-352. 2004
  • Software Defined Radio: What Do We Do with It?.  Springer eBooks. 283-288. 2001

• conference paper

  • An Event-based Formation Control Architecture for UAVs Using an Estimator-based Approach.  2022 IEEE/SICE International Symposium on System Integration (SII). 2022
  • IVS-KOM: A Reference Platform for Heterogeneous ITS Communications.  . 2020
  • 5G-and-Beyond Scalable Machines.  . 2019
  • DF4CRAN: Dataflow Framework for Cloud-RAN Signal Processing.  . 2019
  • Fully parallel window decoder architecture for spatially-coupled LDPC codes.  . 2016
  • Heterogeneous Backhaul for Cloud-Based Mobile Networks.  . 2013
  • Instruction Set Architecture Extensions for a Dynamic Task Scheduling Unit.  . 2012
  • Integration of code optimization and hardware exploration for a VLIW architecture by using fuzzy control system.  . 2011
  • The FUTON prototype: Broadband communication through coordinated multi-point using a novel integrated optical/wireless architecture.  . 2010
  • Code generation for a novel STA architecture by using post-processing backend.  . 2010
  • A Component based Reconfigurable Baseband Architecture.  . 2007
  • A High-Throughput Programmable Decoder for LDPC Convolutional Codes.  . 2007
  • Towards a GBit/s Programmable Decoder for LDPC Convolutional Codes.  . 2007
  • Interconnection Generation for System-on-Chip Design.  . 2006
  • Compiler Scheduling for STA-Processors.  Parallel Computing in Electrical Engineering. 45-60. 2004
  • A new network processor architecture for high-speed communications.  . 2003
  • On the interaction between DSP-algorithms and VLSI-architecture.  . 2002
  • Design methodology for digital signal processing.  . 2002
  • A new scalable DSP architecture for system on chip (SoC) domains.  . 1999