selected publications

• academic article

  • Scalability evaluation of an FPGA-based multi-core architecture with hardware-enforced domain partitioning.  Microprocessors and Microsystems.  38:845-859. 2014
  • Dynamically reconfigurable dataflow architecture for high-performance digital signal processing.  Journal of Systems Architecture.  56:561-576. 2010

• conference paper

  • An asynchronous bus bridge for partitioned multi-soc architectures on FPGAs.  . 2013
  • A multi-core FPGA-based SoC architecture with domain segregation.  . 2012
  • Analysis of a Dynamically Reconfigurable Dataflow Architecture and its Scalable Parallel Extension for Multi-FPGA Platforms.  . 2008