selected publications
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academic article
- A flexible hardware architecture for real-time airborne wavenumber domain SAR processing. Synthetic Aperture Radar, 2012. EUSAR. 9th European Conference on. 28-31. 2012
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chapter
- Design Space Exploration of Media Processors: A Generic VLIW Architecture and a Parameterized Scheduler. Springer eBooks. 254-267. 2007
- RAPANUI: Rapid Prototyping for Media Processor Architecture Exploration. Lecture Notes in Computer Science. 32-40. 2005
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conference paper
- An FPGA architecture for velocity independent backprojection in FMCW-based SAR systems. . 2016
- Synthetic aperture radar with backprojection: A scalable, platform independent architecture for exhaustive FPGA resource utilization. . 2014
- A FPGA architecture for real-time processing of variable-length FFTS. . 2011
- Instruction merging to increase parallelism in VLIW architectures. . 2009
- A parallel hardware architecture for connected component labeling based on fast label merging. . 2008
- On the Design of Scalable Massively Parallel CRC Circuits. . 2007
- Design Space Exploration of Media Processors: A Parameterized Scheduler. . 2007
- Architecture of a flexible on-board real-time SAR-processor. . 2005
- HiBRID-SoC: a multi-core architecture for image and video applications. . 2004
- A high performance digital signal processor for compact realization of real-time synthetic aperture radar systems. . 2003
- Architecture of a hardware module for MPEG-4 shape decoding. . 2003
- A core for ambient and mobile intelligent imaging applications. . 2003
- A fault-tolerant DCT-architecture based on distributed arithmetic. 1993 IEEE International Symposium on Circuits and Systems. 2002
- VLSI architectures for hierarchical block matching algorithms. . 2002
- VLSI architectures for multimedia. . 2002
- Architecture and memory requirements for stand-alone and hierarchical MPEG2 HDTV-decoders with synchronous DRAMs. . 2002