selected publications

• academic article

  • Automated design of error-resilient and hardware-efficient deep neural networks.  Neural Computing and Applications.  32:18327-18345. 2020
  • Optimized Communication Architecture of MPSoCs with a Hardware Scheduler.  International Journal of Embedded and Real-time Communication Systems.  2:1-20. 2011
  • A Scalable VLSI Architecture for Soft-Input Soft-Output Single Tree-Search Sphere Decoding.  IEEE Transactions on Circuits and Systems Ii-express Briefs.  57:706-710. 2010
  • Automatic Generation of Memory Interfaces for ASIPs.  International Journal of Embedded and Real-time Communication Systems.  1:1-23. 2010
  • Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting.  Journal of VLSI signal processing.  43:235-246. 2006
  • Retargetable compilers and architecture exploration for embedded processors.  IEE proceedings.  152:209-209. 2005

• chapter

  • Optimized Communication Architecture of MPSoCs with a Hardware Scheduler.  IGI Global eBooks. 163-180. 2013
  • Automatic Generation of Memory Interfaces for ASIPs.  IGI Global eBooks. 79-100. 2012
  • ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study.  Lecture Notes in Computer Science. 2004
  • Early ISS Integration into Network-on-Chip Designs.  Springer eBooks. 443-452. 2004
  • Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting.  Lecture Notes in Computer Science. 463-473. 2004

• conference paper

  • Ensembles of Long Short-Term Memory Experts for Streaming Data with Sudden Concept Drift.  2021 20th IEEE International Conference on Machine Learning and Applications (ICMLA). 2021
  • Fast SystemC Processor Models with Unicorn.  . 2019
  • Application-Specific Architecture Exploration Based on Processor-Agnostic Performance Estimation.  . 2015
  • A novel reduced-complexity soft-input soft-output MMSE MIMO detector: Algorithm and efficient VLSI architecture.  . 2014
  • A parallel VLSI architecture for Markov chain Monte Carlo based MIMO detection.  . 2013
  • Optimized communication architecture of MPSoCs with a hardware scheduler: A system view.  . 2010
  • Automatic generation of memory interfaces.  . 2009
  • High-level modelling and exploration of coarse-grained re-configurable architectures.  . 2008
  • High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures.  2008 Design, Automation and Test in Europe. 2008
  • Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors.  Proceedings. 2007
  • Design space exploration of partially re-configurable embedded processors.  Design, Automation, and Test in Europe. 319-324. 2007
  • Instruction Set Customization of Application Speci.c Processors for Network Processing: A Case Study.  . 2006
  • Optimization Techniques for ADL-Driven RTL Processor Synthesis.  . 2006
  • C Compiler Retargeting Based on Instruction Semantics Models.  Design, Automation, and Test in Europe. 2005
  • Fine-grained application source code profiling for ASIP design.  . 2005
  • A methodology and tool suite for C compiler generation from ADL processor models.  Proceedings Design, Automation and Test in Europe Conference and Exhibition. 2004
  • A methodology and tool suite for C compiler generation from ADL processor models.  . 21276-21276. 2004
  • A system level processor/communication co-exploration methodology for multi-processor system-on-chip platforms.  . 21256. 2004
  • RTL processor synthesis for architecture exploration and implementation.  . 30156. 2004
  • A modular simulation framework for architectural exploration of on-chip interconnection networks.  . 2003
  • A modular simulation framework for architectural exploration of on-chip interconnection networks.  . 2003