selected publications

• academic article

  • A Memory Centric Architecture of the Link Assessment Algorithm in Large Graphs.  IEEE design & test.  35:7-15. 2018
  • An energy efficient weakly programmable MIMO detector architecture.  Advances in Radio Science.  11:131-136. 2013

• conference paper

  • Efficient Hardware Approximation for Bit-Decomposition Based Deep Neural Network Accelerators.  . 2022
  • An Energy Efficient 3D-Heterogeneous Main Memory Architecture for Mobile Devices.  . 2020
  • A new architecture for high throughput, low latency NB-LDPC check node processing.  . 2015
  • A quantitative cross-architecture study of morphological image processing on CPUs, GPUs, and FPGAs.  . 2015
  • Advanced hardware architecture for soft decoding Reed-Solomon codes.  . 2014
  • A scalable multi-ASIP architecture for standard compliant trellis decoding.  . 2011
  • SPP1148 booth: Application-specific reconfigurable processors.  . 2008
  • Evaluation of High Throughput Turbo-Decoder Architectures.  . 2007
  • A high-speed MAP architecture with optimized memory size and power consumption.  . 2002