selected publications

• academic article

  • MORPHEUS.  ACM Transactions in Embedded Computing Systems.  12:1-33. 2013
  • Real-time Car-to-X Communication Security and E/E Architecture Integration.  ATZelektronik worldwide.  2012
  • A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip.  International Journal of Reconfigurable Computing.  2009:1-11. 2009

• chapter

  • Hybrid Prototyping for Manycore Design and Validation.  Lecture Notes in Computer Science. 2019
  • Advances in Avionic Platforms: Multi-core Systems.  . 2018
  • Towards Design and Integration of a Vehicle-to-X Based Adaptive Cruise Control.  Springer eBooks. 87-99. 2012
  • DodOrg—A Self-adaptive Organic Many-core Architecture.  . 353-368. 2011
  • Development and Synthesis of Adaptive Multi-grained Reconfigurable Hardware Architecture for Dynamic Function Patterns.  Springer eBooks. 3-24. 2010
  • Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures.  Lecture Notes in Computer Science. 584-589. 2001
  • DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communication Applications.  Springer eBooks. 312-321. 2000
  • Field Programmable Communication Emulation and Optimization for Embedded System Design.  Lecture Notes in Computer Science. 2000

• conference paper

  • Model-based Attack Tree Generation for Cybersecurity Risk-Assessments in Automotive.  . 2021
  • Towards an On-Demand Redundancy Concept for Autonomous Vehicle Functions using Microservice Architecture.  . 2020
  • Automated Assessment of E/E-Architecture Variants Using an Integrated Model- and Simulation-Based Approach.  SAE technical paper series. 2019
  • Cross-Layer Behavioral Modeling and Simulation of E/E-Architectures using PREEvision and Ptolemy II : [extended version].  Summer Computer Simulation Conference. 18. 2019
  • LISPARC: Using an architecture description language approach for modelling an adaptive processor microarchitecture.  . 2012
  • Virtualized on-chip distributed computing for heterogeneous reconfigurable multi-core systems.  Design, Automation, and Test in Europe. 280-283. 2012
  • HoneyComb: A multi-grained dynamically reconfigurable runtime adaptive hardware architecture.  . 2011
  • Comparative Application of Real-Time Verification Methods to an Automotive Architecture.  HAL (Le Centre pour la Communication Scientifique Directe). 2010
  • Mixed-Signal Diverse Redundant System for Safety Critical Applications in FPGA.  . 2010
  • Semi-Automatic Toolchain for Reconfigurable Multiprocessor Systems-on-Chip: Architecture Development and Application Partitioning.  Field Programmable Gate Arrays. 286. 2010
  • Dynamic reconfigurable mixed-signal architecture for safety critical applications.  . 2009
  • Retargeting, Evaluating, and Generating Reconfigurable Array-Based Architectures.  . 2008
  • Combining Rewriting-Logic, Architecture Generation, and Simulation to Exploit Coarse-Grained Reconfigurable Architectures.  . 2008
  • A system architecture for reconfigurable trusted platforms.  . 2008
  • Design of a HW/SW communication infrastructure for a heterogeneous reconfigurable processor.  . 2008
  • Communication Architectures for Dynamically Reconfigurable FPGA Designs.  . 2007
  • Architecture, memory and interface technology integration of an industrial/ academic configurable system-on-chip (CSoC).  . 2003
  • An industrial/academic configurable system-on-chip project (CSoC): coarse-grain XPP-/Leon-based architecture integration.  Design, Automation, and Test in Europe. 11120-11121. 2003
  • Communication performance models for architecture-precise prototyping of real-time embedded systems.  . 2003
  • An embedded accelerator for real-time image processing.  . 2002
  • A partitioning programming environment for a novel parallel architecture.  . 2002
  • Design and implementation of a coarse-grained dynamically reconfigurable hardware architecture.  . 2002
  • Automated communication synthesis for architecture-precise rapid prototyping of real-time embedded systems.  . 2002
  • An Application-Tailored Dynamically Reconfigurable Hardware Architecture for Digital Baseband Processing.  Symposium on Integrated Circuits and Systems Design. 341-346. 2000