selected publications

• academic article

  • Proceedings of the 29th International Conference on Architecture of Computing Systems -- ARCS 2016 - Volume 9637.  .  2016
  • A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime.  International Journal of Reconfigurable Computing.  2009:1-10. 2009

• blog posting

  • Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators.  arXiv (Cornell University). 2020

• chapter

  • Interconnect Architectures for 3D Technologies.  Springer eBooks. 27-47. 2022
  • Network Synthesis and SoC Floor Planning.  Springer eBooks. 323-361. 2022
  • StreamGrid - An AXI-Stream-Compliant Overlay Architecture.  Springer eBooks. 156-170. 2021
  • Search & Update Optimization of a B $$^+$$ Tree in a Hardware Aided Semantic Web Database System.  Lecture Notes in Electrical Engineering. 172-182. 2017
  • DynaCORE—Dynamically Reconfigurable Coprocessor for Network Processors.  Springer eBooks. 335-354. 2010
  • A Dynamically Reconfigurable Function-Unit for Error Detection and Correction in Mobile Terminals.  Lecture Notes in Computer Science. 2004
  • Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures.  Lecture Notes in Computer Science. 584-589. 2001

• conference paper

  • A Flexible and Scalable Reconfigurable FPGA Overlay Architecture for Data-Flow Processing.  . 2023
  • Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators.  . 2021
  • Hardware-Accelerated Index Construction for Semantic Web.  . 2018
  • An architectural template for composing application specific datapaths at runtime.  . 2015
  • MONSUN II: A small and inexpensive AUV for underwater swarms.  German Conference on Robotics. 1-6. 2012
  • On the design parameters of runtime reconfigurable systems.  . 2008
  • SPP1148 booth: Network processors.  . 2008
  • Communication Architectures for Dynamically Reconfigurable FPGA Designs.  . 2007
  • Design and implementation of a coarse-grained dynamically reconfigurable hardware architecture.  . 2002
  • An Application-Tailored Dynamically Reconfigurable Hardware Architecture for Digital Baseband Processing.  Symposium on Integrated Circuits and Systems Design. 341-346. 2000