selected publications

• academic article

  • A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement.  IEEE Transactions on Very Large Scale Integration Systems.  27:2375-2386. 2019
  • Optimized Communication Architecture of MPSoCs with a Hardware Scheduler.  International Journal of Embedded and Real-time Communication Systems.  2:1-20. 2011

• chapter

  • Optimized Communication Architecture of MPSoCs with a Hardware Scheduler.  IGI Global eBooks. 163-180. 2013

• conference paper

  • Optimized communication architecture of MPSoCs with a hardware scheduler: A system view.  . 2010