A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement Academic Article

authors

Castrillón, Jerónimo

publication date

October 1, 2019

has subject area

published in

IEEE Transactions on Very Large Scale Integration Systems Journal

Digital Object Identifier (DOI)

https://doi.org/10.1109/tvlsi.2019.2918385

start page

2375

end page

2386

volume

27

issue

10