IEEE Transactions on Very Large Scale Integration Systems Journal

publication venue for

A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement. 27:2375-2386. 2019
Efficient Architecture for Soft-Input Soft-Output Sphere Detection With Perfect Node Enumeration. 24:2932-2945. 2016
CGADL: An Architecture Description Language for Coarse-Grained Reconfigurable Arrays. 17:1247-1259. 2009

International Standard Serial Number (ISSN)

1063-8210